Browsing Theses by Author "Ravishankar, Chirag"
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Guarded Evaluation: An Algorithm for Dynamic Power Reduction in FPGAs
Ravishankar, Chirag (University of Waterloo, 2012-04-25)Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing ...