dc.contributor.author | Gholamian, Sina | |
dc.date.accessioned | 2012-08-29 16:15:11 (GMT) | |
dc.date.available | 2012-08-29 16:15:11 (GMT) | |
dc.date.issued | 2012-08-29T16:15:11Z | |
dc.date.submitted | 2012 | |
dc.identifier.uri | http://hdl.handle.net/10012/6906 | |
dc.description.abstract | This thesis presents a link-level latency analysis for real-time network-on-chip interconnects that use priority-based wormhole switching. This analysis incorporates both direct and indirect
interferences from other traffic flows, and it leverages pipelining and parallel transmission of data across the links. The resulting link-level analysis provides a tighter worst-case upper-bound than existing techniques, which we verify with our analysis and simulation experiments. Our
experiments show that on average, link-level analysis reduces the worst-case latency by 28.8%, and improves the number of flows that are schedulable by 13.2% when compared to previous work. | en |
dc.language.iso | en | en |
dc.publisher | University of Waterloo | en |
dc.subject | Network-on-Chip | en |
dc.subject | Real-Time | en |
dc.title | A Link-Level Communication Analysis for Real-Time NoCs | en |
dc.type | Master Thesis | en |
dc.pending | false | en |
dc.subject.program | Electrical and Computer Engineering | en |
uws-etd.degree.department | Electrical and Computer Engineering | en |
uws-etd.degree | Master of Applied Science | en |
uws.typeOfResource | Text | en |
uws.peerReviewStatus | Unreviewed | en |
uws.scholarLevel | Graduate | en |