Test Chip Design for Process Variation Characterization in 3D Integrated Circuits
Abstract
A test chip design is presented for the characterization of process variations and Through
Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de-
signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries
process through CMC microsystems. The test chip takes advantage of the architecture
of 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a device
array density of 40.94 m2 per device. The design also has a high spatial resolution and
measurement delity compared to similar 2D variation characterization test structures.
Background leakage subtraction and radial ltering are two techniques that are ap-
plied to the chip's measurements to reduce its error further for subthreshold device current
measurements and stress-induced mobility measurements, respectively. Experimental mea-
surements are be taken from the chip using a custom PCB measurement setup once the
chip has returned from fabrication.
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Cite this version of the work
Conor O'Sullivan
(2013).
Test Chip Design for Process Variation Characterization in 3D Integrated Circuits. UWSpace.
http://hdl.handle.net/10012/7888
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