Novel MEMS Tunable Capacitors with Linear Capacitance-Voltage Response Considering Fabrication Uncertainties

Abstract

Electrostatically actuated parallel-plate MEMS tunable capacitors are desired elements for different applications including sensing, actuating and communications and RF (radio frequency) engineering for their superior characteristics such as quick response, high Q-factor and small size. However, due to the nature of their coupled electrostatic-structural physics, they suffer from low tuning range of 50% and have nonlinear capacitance-voltage (C-V) responses which are very sensitive to the voltage change near pull-in voltage. Numerous studies in the literature introduce new designs with high tunability ranging from 100% to over 1500%, but improvement of the nonlinearity and high sensitivity of the capacitor response have not received enough attention. In this thesis, novel highly tunable capacitors with high linearity are proposed to reduce sensitivity to the voltage changes near pull-in. The characteristic equations of a perfectly linear capacitor are first derived for two- and three-plate capacitors to obtain insight for developing linear capacitance-voltage responses. The devices proposed in this research may be classified into three categories: designs with nonlinear structural rigidities, geometric modifications and flexible moving electrodes. The concept of nonlinear supporting beams is exploited to develop parallel-plate capacitors with partially linear C-V curves. Novel electrodes with triangular, trapezoidal, butterfly, zigzag and fishbone shapes and structural/geometric nonlinearities are used to increase the linearity and tuning ratio of the response. To investigate the capacitors' behavior, an analytical approximate model is developed which can drastically decrease the computation time. The model is ideal for early design and optimization stages. Using this model, design variables are optimized for maximum linearity of the C-V responses. The results of the proposed modeling approach are verified by ANSYS FEM simulations and/or experimental data. When the fabrication process has dimensional limitations, design modifications and geometric enhancements are implemented to improve the linearity of the C-V response. The design techniques proposed in this thesis can provide tunabilities ranging from 80% to over 350% with highly linear regions in resulting C-V curves. Due to the low sensitivity of the capacitance to voltage changes in new designs, the entire tuning range is usable. Furthermore, the effect of fabrication uncertainties on parallel-plate capacitors performance is studied and a sensitivity analysis is performed to find the design variables with maximum impact on the C-V curves. An optimization method is then introduced to immunize the design against fabrication uncertainties and to maximize the production yield for MEMS tunable capacitors. The method approximates the feasible region and the probability distribution functions of the design variables to directly maximize the yield. Numerical examples with two different sets of design variables demonstrate significant increase in the yield. The presented optimization method can be advantageously utilized in design stage to improve the yield without increasing the fabrication cost or complexity.